In recent years, semiconductor integrated circuits have been widely used in various devices such as electronic devices. The semiconductor integrated circuits such as processors consume power, for example, when executing a computing operation.
The power consumed by the semiconductor integrated circuit varies depending on, for example, the computing operation performed at that time. For example, also in the clock gating technique for decreasing power consumption, the consumed power considerably varies between clock-disabled time and clock-enabled time.
Current consumed by the semiconductor integrated circuit also varies in a similar manner to the consumed power. This generates di/dt noise and thus causes voltage fluctuations in the power supply wiring and the ground wiring in the semiconductor integrated circuit. Note that a semiconductor element of the semiconductor integrated circuit operates fast at a high operating voltage and slowly at a low operating voltage. If voltage fluctuations occur owing to consumed current fluctuations, the speed of the semiconductor element also fluctuates.
For example, since a semiconductor integrated circuit such as a processor operates under timing constraints defined based on a clock frequency, an occurrence of a voltage drop causes timing constraint violation, and thus an error might occur.
Under such circumstances, clock frequency control is known in which voltage fluctuations are tracked to modulate a clock frequency. In an example of proposed clock frequency control, delay deterioration attributable to the voltage fluctuations is tracked to lower the clock frequency, and the timing constraint violation is thereby avoided.
Examples of proposed technologies in the related art include a technology by which delay variation in a semiconductor element is compensated for in such a manner that supply voltage fluctuations are detected.
Another example of proposed clock frequency control methods in the related art is a method by which a change in the oscillation frequency of a ring oscillator is converted into a delay variation value to modulate, based on the amount of correction for the delay variation, a clock frequency of a phase locked loop (PLL).
However, since the method employs feedforward control, it takes time to measure the oscillation frequency of the ring oscillator, and thus only delay variation attributable to low-frequency voltage fluctuations is addressed.
Another example of the proposed clock frequency control is a method by which, based on setup slack (setup constraint margin) measured by a critical path monitor, a clock frequency of a PLL is modulated to control an amount of setup slack.
However, since this method employs feedback control, a filter is used for stabilizing a system so as to decrease a control gain and thus to delay total response. As a result, this retards a response to address a disturbance factor, and thus only delay variation attributable to low-frequency voltage fluctuations is addressed.
Meanwhile, a semiconductor integrated circuit (package containing a semiconductor chip) has a resonance frequency of, for example, tens of MHz to hundreds of MHz, and thus the voltage at a sudden consumed-current increase fluctuates in a band from tens of MHz to hundreds of MHz.
Accordingly, in the example of the clock frequency control method described above, for example, the control is not performed in time for delay variation in the resonance frequency band of the semiconductor integrated circuit package. It is thus difficult to fully compensate for the delay variation.
Further, for example, even though the clock frequency control is performed on the voltage fluctuations in the band from tens of MHz to hundreds of MHz, the frequency modulation does not track the voltage fluctuations, and thus the frequency is undesirably lowered. In other words, it is difficult to avoid a disadvantage of the clock frequency control, in voltage fluctuations in a particular frequency band.
The followings are reference documents:    [Document 1] Japanese Laid-open Patent Publication No. 2008-099163,    [Document 2] Japanese Laid-open Patent Publication No. 2005-102197,    [Document 3] U.S. Pat. No. 8,222,936, Specification; and    [Document 4] Charles R. Lefurgy et al., “Active Management of Timing Guardband to Save Energy in POWER7 (registered trademark)”, MICRO 44, pp. 1-11, Dec. 3-7, 2011.